1. Field of the Invention
The present invention relates to a shift register. Specifically, the present invention relates to a shift register composed of thin film transistors (hereinafter referred to as TFTs) and to a method of driving the shift register.
2. Description of the Related Art
Shift registers, which receive a clock pulse and a start pulse to output pulses (sampling pulses) sequentially, are used in various circuits. In a display device which has a plurality of pixels arranged to form a matrix, shift registers are particularly used as a gate signal line driving circuit and a gate signal line driving circuit for selecting pixels and inputting signals to the selected pixels.
An example of the structure of a general shift register is shown in FIG. 5. The shift register has first to r-th (r is a natural number equal to or larger than 3) stages. Each stage is composed of a first clocked inverter CKINV1, a second clocked inverter CKINV2, and an inverter INV.
The i-th (i is a natural number equal to or less than r) stage is referred to as SR_i. A first clocked inverter, a second clocked inverter, and an inverter that constitute the i-th stage are referred to as CKINV1_i, CKINV2_i, and INV-i, respectively.
In the first stage SR_1, a start pulse SP is inputted from the external to an input terminal of the first clocked inverter CKINV1_1, and an output terminal of the first clocked inverter CKINV1_1 is connected to an input terminal of the inverter INV_1 and to an output terminal of the second clocked inverter CKINV2_1. An input terminal of the second clocked inverter CKINV2_1 is connected to an output terminal of the inverter INV_1. The output terminal of the inverter INV_1 serves as the output terminal of the first stage SR_1.
In the second stage SR_2, an input terminal of the first clocked inverter CKINV1_2 is connected to an output terminal of the inverter INV_1 in the first stage SR_1, and an output terminal of the first clocked inverter CKINV1_2 is connected to an input terminal of the inverter INV_2 and to an output terminal of the second clocked inverter CKINV2_2. An input terminal of the second clocked inverter CKINV2_2 is connected to an output terminal of the inverter INV_2. The output terminal of the inverter INV_2 serves as the output terminal of the second stage SR_2.
Generally, in a j-th (i is a natural number equal to or larger than 2, and equal to or smaller than r) stage, an input terminal of the first clocked inverter CKINV1_j is connected to an outputted terminal of the inverter INV_j−1 in the (j−1)-th stage SR_j−1, and an output terminal of the first clocked inverter CKINV1_j is connected to an input terminal of the inverter INV_j and to an output terminal of the second clocked inverter CKINV2_j. An input terminal of the second clocked inverter CKINV2_j is connected to an output terminal of the inverter INV_j. The output terminal of the inverter INV_j serves as the output terminal of the j-th stage.
When a start pulse SP is inputted to the first stage, the shift register composed of the first stage circuit SR_1 to the r-th stage circuit SR_r that are structured as above sequentially outputs shifted pulses S_1 to S_r from the output terminals of the first stage circuit SR_1 to the r-th stage circuit SR_r in sync with a clock pulse CK and an inverted clock pulse CKB which is obtained by inverting the polarity of the clock pulse CK. The clock pulse CK and inverted clock pulse CKB are inputted to the first clocked inverters CKINV1 and second clocked inverters CKINV2 of the first to r-th stages.
FIG. 4 is an example of detailed circuit diagram of the first clocked inverter CKINV1, second clocked inverter CKINV2, and inverter INV that constitute each stage in the shift register with the structure as shown in FIG. 5.
Vdd represents a high power supply electric potential and Vss represents a low power supply electric potential. Here, the high power supply electric potential Vdd is set higher than the low power supply electric potential Vss. The electric potential difference between the high power supply electric potential Vdd and the low power supply electric potential Vss corresponds to the power supply voltage of the shift register.
The first clocked inverter CKINV1 is composed of p-channel TFTs 501a and 501b and n-channel TFTs 501d and 501c. In this specification, a p-channel TFT and n-channel TFT of the first clocked inverter CKINV1 that receive a clock pulse CK or an inverted clock pulse CKB through their gate electrodes are denoted by 501a and 501d, respectively. Then gate electrodes of the p-channel TFT 501b and n-channel TFT 501c are connected to the input terminal of the first clocked inverter CKINV1.
If a clock pulse CK is to be inputted to the gate electrode of the p-channel TFT 501a. an inverted clock pulse CKB is inputted to the gate electrode of the n-channel TFT 501d. On the other hand, if an inverted clock pulse CKB is to be inputted to the gate electrode of the p-channel TFT 501a, a clock pulse CK is inputted to the gate electrode of the n-channel TFT 501d. 
The source electrode of the p-channel TFT 501a is kept at the same level as the high power supply electric potential Vdd and the drain electrode thereof is connected to the source electrode of the p-channel TFT 501b. The drain electrode of the p-channel TFT 501b is connected to the drain electrode of the n-channel TFT 501c and the source electrode of the n-channel TFT 501c is connected to the drain electrode of the n-channel TFT 501d. The source electrode of the n-channel TFT 501d is kept at the same level as the low power supply electric potential Vss. The gate electrodes of the p-channel TFT 501b and the n-channel TFT 501c serve as the input terminal of the first clocked inverter CKINV1. The drain electrodes of the p-channel TFT 501b and the n-channel TFT 501c serve as the output terminal of the first clocked inverter CKINV1.
The second clocked inverter CKINV2 is composed of p-channel TFTs 502a and 502b and n-channel TFTs 502d and 502c. In this specification, a p-channel TFT and an n-channel TFT of the second clocked inverter CKINV2 which receive a clock pulse CK or an inverted clock pulse CKB through their gate electrodes are denoted by 502a and 502d, respectively. Further, gate electrodes of the p-channel TFT 502b and n-channel TFT 502c are connected to the output terminal of the inverter INV.
If a clock pulse CK is to be inputted to the gate electrode of the p-channel TFT 501a that constitutes the first clocked inverter CKINV1, an inverted clock pulse CKB is inputted to the gate electrode of the p-channel TFT 502a that constitutes the second clocked inverter CKINV2 and a clock pulse CK is inputted to the gate electrode of the n-channel TFT 502d. On the other hand, if an inverted clock pulse CKB is to be inputted to the gate electrode of the p-channel TFT 501a that constitutes the first clocked inverter CKINV1, a clock pulse CK is inputted to the gate electrode of the p-channel TFT 502a that constitutes the second clocked inverter CKINV2 and an inverted clock pulse CKB is inputted to the gate electrode of the n-channel TFT 502d. 
The source electrode of the p-channel TFT 502a is kept at the same level as the high power supply electric potential Vdd and the drain electrode thereof is connected to the source electrode of the p-channel TFT 502b. The drain electrode of the p-channel TFT 502b is connected to the drain electrode of the n-channel TFT 502c and the source electrode of the n-channel TFT 502c is connected to the drain electrode of the n-channel TFT 502d. The source electrode of the n-channel TFT 502d is kept at the same level as the low power supply electric potential Vss. The drain electrodes of the p-channel TFT 502b and n-channel TFT 502c serve as the output terminal of the second clocked inverter CKINV2.
The inverter INV is composed of a p-channel TFT 503a and an n-channel TFT 503b. A source electrode of the p-channel TFT 503a is kept at the same level as the high power supply electric potential Vdd and a drain electrode of the p-channel TFT 503a is connected to a drain electrode of the n-channel TFT 503b. A source electrode of the n-channel TFT 503b is kept at the same level as the low power supply electric potential Vss. Gate electrodes of the p-channel TFT 503a and n-channel TFT 503b serve as the input terminal of the inverter INV. The drain electrodes of the p-channel TFT 503a and n-channel TFT 503b serve as the output terminal of the inverter INV.
If a gate electrode of a p-channel TFT 501a_i of the first clocked inverter CKINV1_i of the i-th (i is a natural number) stage receives a clock pulse CK, an inverted clock pulse CKB is inputted to a gate electrode of a p-channel TFT 501a_i−1 of the first clocked inverter CKINV1_i−1 of the (i−1)-th stage.
P-channel TFTs 501a and 501b and n- N-channel TFTs 501c and 501d that constitute the first clocked inverter CKINV1_i (i is a natural number) of the i-th stage are denoted by 501a_i and 501b_i, and 501c_i and 501d_i, respectively. Similarly, p-channel TFTs 502a and 502b and n-channel TFTs 502c and 502d that constitute the second clocked inverter CKINV2_i of the i-th stage are denoted by 502a_i and 502b_i, and 502c—i and 502d_i. respectively. An n-channel TFT 503a and p-channel TFT 503b that constitute the inverter INV_i of the i-th stage are denoted by 503a_i and 503b_i, respectively.
FIG. 7 is a timing chart showing an ideal method of driving the shift register structured as shown in FIGS. 4 and 5. The concrete operation thereof are described below.
The shift register receives a clock pulse CK, an inverted clock pulse CKB obtained by inverting the polarity of the clock pulse CK, and a start pulse SP. In the first clocked inverter CKINV1_1 of the first stage SR_1, an inverted clock pulse CKB is inputted to the gate electrode of the p-channel TFT 501a_1 and a clock pulse CK is inputted to the gate electrode of the n-channel TFT 501d_1. A start pulse SP is inputted to the gate electrodes of the p-channel TFT 501b_1 and n-channel TFT 501c_1 of the first clocked inverter CKINV1_1.
The relation of the start pulse SP and the clock pulse CK and inverted clock pulse CKB is as shown in the timing chart of FIG. 7.
A start pulse SP is inputted to the input terminal of the first clocked inverter CKINV1_1 of the first stage SR_1. In other words, the first clocked inverter CKINV1_1 receives “Hi” electric potential upon input of the start pulse SP, and receives a clock pulse CK and an inverted clock pulse CKB as well. The n-channel TFTs 501c_1 and 501d_1 of the first clocked inverter CKINV1_1 are turned ON. The electric potential of the output terminal of the first clocked inverter CKINV1_1 is thus set to the low power supply electric potential Vss. That is, an output SB_1 of the first clocked inverter CKINV1_1 of the first stage is “Lo” electric potential. At this point, the p-channel TFT 502a_1 and n-channel TFT 502d_1 of the second clocked inverter CKINV2_1 of the same stage are turned OFF by a clock pulse CK and inverted clock pulse CKB that are inputted to the gate electrodes of the TFTs 502a_1 and 502d_1.
On the other hand, both the p-channel TFT 501a_2 and n-channel TFT 501d_2 of the first clocked inverter CKINV1_2 of the second stage are turned OFF by a clock pulse CK and inverted clock pulse CKB that are inputted to the gate electrodes of the TFTs 501a_2 and 501d_2.
The p-channel TFT 502a_2 and n-channel TFT 502d_2 of the second clocked inverter CKINV2_2 are both turned ON by a clock pulse CK and inverted clock pulse CKB that are inputted to the gate electrodes of the TFTs 502a_2 and 502d_2, and “Lo” electric potential is inputted to the input terminal of the second clocked inverter CKINV2_2. Therefore, the high power supply electric potential Vdd is outputted from the output terminal of the second clocked inverter CKINV2_2. In other words, the second clocked inverter CKINV2_2 outputs “Hi” electric potential.
Next, a clock pulse CK and an inverted clock pulse CKB turns the n-channel TFT 501d_1 into OFF in the first clocked inverter CKINV1_1 of the first stage SR_1. On the other hand, the n-channel TFT 502d_1 is turned ON in the second clocked inverter CKINV2_1.
The output SB_1 of the first clocked inverter CKINV1_1 is inputted to the input terminal of the second clocked inverter CKINV2_1 through the inverter INV_1. In other words, a signal obtained by inverting the polarity of the output SB_1 of the first clocked inverter CKINV1_1 is inputted to the input terminal of the second clocked inverter CKINV2_1. This input signal turns the n-channel TFT 502c_1 of the second clocked inverter CKINV2_1 ON. In this way, the output terminal of the second clocked inverter CKINV2_1 is set to the low power supply electric potential Vss. That is, the output SB_1 of the second clocked inverter CKINV2_1 is “Lo” electric potential.
On the other hand, “Hi” electric potential is inputted from the first stage SR_1 to the input terminal of the first clocked inverter CKINV1_2 of the second stage. A clock pulse CK and an inverted clock pulse CKB turn the n-channel TFT 501d_2 ON. Thus, the output terminal of the first clocked inverter CKINV1_2 of the second stage is set to the low power supply electric potential Vss, and the output SB_2 of the first clocked inverter CKINV1_2 of the second stage obtains “Lo” electric potential.
A clock pulse CK and an inverted clock pulse CKB again turn the p-channel TFT 501a_1 of the first clocked inverter of the first stage ON. At this point, a start pulse SP is not inputted and therefore the p-channel TFT 501b_1 of the first clocked inverter is also ON. Accordingly, the output terminal of the first clocked inverter CKINV1_1 of the first stage is set to the high power supply electric potential Vdd and the output SB_1 of the first clocked inverter obtains “Hi” electric potential.
The outputs of the first clocked inverter CKINV1 and second clocked inverter CKINV2 are changed as described above. The outputs S of the respective stages are thus outputted while each output is shifted sequentially from the inputted start pulse SP by half a cycle of clock pulse CK. The shift register shown in FIG. 4 outputs pulses in this way.
In contrast with the shift register structured as shown in FIG. 4, there is a shift register that outputs a pulse obtained from NAND operation of output signals S of adjacent stages. An example of this shift register is shown in FIG. 10. In FIG. 10, components which are identical with those in FIG. 4 are denoted by the same reference symbols and explanations thereof will be omitted.
An output S_i of the i-th stage circuit SR_i and an output S_i+1 of the (i+1)-th ((i+1) is a natural number equal to or smaller than r) stage circuit SR_i+1 are inputted to an i-th NAND circuit NAND_i. The i-th NAND circuit NAND_i outputs an i-th pulse SMP_i. The pulse SMP_i is an output pulse of the shift register.
FIG. 11 is a timing chart for a method of driving the shift register shown in FIG. 10. The operation in FIG. 10 is identical with the operation in FIG. 7 until sequentially outputting shifted pulses S_1 to S_r from the output terminals of the first stage circuit SR_1 to the r-th stage circuit SR_r is completed. Thereafter outputs of adjacent stages are inputted to the respective NAND circuits, NAND_1 to NAND_r−1, and pulses SMP_1 to SMP_r−1 are outputted sequentially. In this way, the shift register shown in FIG. 10 outputs pulses.
The shift register shown in FIGS. 4, 5 and 10 needs a small number of elements to construct a circuit. Accordingly, only a small load capacity is required and the operation at high frequency is relatively easy.
In general, a shift register operates with the power supply voltage set almost equal to the amplitude voltage of signals of clock pulse and start pulse. The power supply voltage of a shift register is usually set to about 10 V.
Pulse signals such as clock pulses and start pulses to be inputted to a shift register are usually outputted by a pulse signal controlling circuit that is formed on a single crystal IC substrate. The pulse signal controlling circuit normally outputs a control signal with an amplitude voltage of about 3.3 V. The amplitude voltage of a pulse signal outputted from a pulse signal generating circuit is usually increased by a level shifter or the like to reach about the same level as the power supply voltage of the shift register before inputted to the shift register.
Now, assume that the signal voltage of a pulse signal to be inputted to a shift register is not increased by a level shifter or the like. This corresponds to the case in which the power supply voltage (corresponding to the electric potential difference between the high power supply electric potential Vdd and the low power supply electric potential Vss) of the elements that constitute the shift register of FIG. 4, namely, the power supply electric potential of the shift register is larger than the amplitude voltage of start pulse SP and clock pulse CK.
The operation of the shift register in this case will be described with reference to a timing chart of FIG. 6. For the circuit structure of the shift register, FIG. 4 is referred to. Assume that the power supply voltage of the shift register is 10 V (the high power supply electric potential Vdd is 10 V and the low power supply electric potential Vss is 0 V) and the amplitude voltage of pulse signals such as clock pulses and start pulses is 3.0 V for the sake of explanation. Then the electric potential which is corresponding to “Lo” of the pulse signals (the lowest electric potential) is set to 3.5 V and the electric potential which is corresponding to “Hi” of the pulse signals (the highest electric potential) is set to 6.5 V.
The first clocked inverter CKINV1 is focused. There is considered a case in which a clock pulse CK and an inverted clock pulse CKB are inputted thereto and the gate electrode of the p-channel TFT 501a receives the electric potential which is corresponding to “Hi”, in this case, 6.5 V and, at the same time, the gate electrode of the n-channel TFT 501d receives the electric potential which is corresponding to “Lo”, in this case, 3.5 V. In this state, the p-channel TFT 501a and the n-channel TFT 501d are ideally both turned OFF. However, the following problems arise because the amplitude voltage of clock pulse CK and inverted clock pulse CKB is smaller than the power supply voltage.
In the p-channel TFT 501a, the electric potential of its source electrode exceeds the electric potential of the gate electrode thereof. In this example, the electric potential of the source electrode of the p-channel TFT 501a is 10 V that is the high power supply electric potential Vdd and the electric potential of the gate electrode thereof is 6.5 V that is “Hi” electric potential of the clock pulse CK or inverted clock pulse CKB, and the electric potential difference between the source electrode and the gate electrode is 3.5 V. If the threshold voltage of the p-channel TFT 501a (the electric potential of the gate electrode with respect to the electric potential of the source electrode in the p-channel TFT) is −3.5 V or more, in other words, if the absolute value of the threshold voltage of the p-channel TFT 501a is smaller than 3.5 V, the p-channel TFT 501a is undesirably turned ON to make its source-drain conductive.
Similarly, in the n-channel TFT 501d, the electric potential of its source electrode is below the electric potential of the gate electrode thereof. In this example, the electric potential of the source electrode of the n-channel TFT 501d is 0 V that is the low power supply electric potential Vss and the electric potential of the gate electrode thereof is 3.5 V that is “Lo” electric potential of the clock pulse CK or inverted clock pulse CKB, and the electric potential difference between the source electrode and the gate electrode is 3.5 V. If the threshold voltage of the n-channel TFT 501d (the electric potential of the gate electrode with respect to the electric potential of the source electrode in the n-channel TFT) is 3.5 V or less, the n-channel TFT 501d is undesirably turned ON.
Areas indicated by broken lines in the timing chart show the operation of the shift register when the TFTs that should be OFF are turned ON due to the problems described above.
At this point, if a start pulse SP is inputted to the input terminal of the first clocked inverter CKINV1_1 of the first stage SR_1 as shown in the timing chart, the first clocked inverter CKINV1_1 outputs a signal SB_1 in sync with the clock pulse CK and inverted clock pulse CKB.
The output from the inverter INV_1 of the first stage SR_1 (denoted by S_1 in the drawing) is inputted to the first clocked inverter CKINV1_2 of the second stage SR_2.
If the pulse signal S_1 outputted from the first stage SR_1 is inputted to the input terminal of the first clocked inverter CKINV1_2 of the second stage SR_2 and the n-channel TFT 501d_2 that should be OFF is turned ON due to the problems described above, leak current flows through the n-channel TFT 501c_2 and n-channel TFT 501d_2. While this leak current is flowing, the output electric potential SB_2 of the first clocked inverter CKINV1_2 becomes lower than the high power supply electric potential Vdd (indicated by a broken line 401n in FIG. 6).
On the other hand, if the pulse signal S_1 outputted from the first stage SR_1 is not inputted to the input terminal of the first clocked inverter CKINV1_2 of the second stage SR_2 and the p-channel TFT 501a_2 that should be OFF is turned ON due to the problems described above, leak current flows through the p-channel TFT 501a_2 and p-channel TFT 501b_2. While this leak current is flowing, the output electric potential SB_2 of the first clocked inverter CKINV1_2 becomes higher than the low power supply electric potential Vss (indicated by a broken line 401p in FIG. 6).
The similar phenomenon takes place in the third stage SR_3 and its subsequent stages and the leak current causes the output electric potential SB of the first clocked inverter CKINV1 of the stage in question to fluctuate from the ideal operation shown in the timing chart of FIG. 7.
As described above, if a pulse is inputted to the input terminal of the first clocked inverter CKINV1 while the p-channel TFT 501a and n-channel TFT 501d that should be OFF are turned ON, current flows through the n-channel TFTs 501c and 501d (this current is hereinafter called as leak current of n-channel TFTs) to output a lower electric potential than the intended output electric potential Vdd.
Also, if a pulse is not inputted to the input terminal of the first clocked inverter CKINV1 while the TFT 501a and TFT 501d that should be OFF are turned ON, current flows through the TFTs 501a and 501b (this current is hereinafter called as leak current of p-channel TFTs) to output a higher electric potential than the intended output electric potential Vss.
When the leak current is large, it is impossible to make pulses of outputs SB shift.
In this way, the shift register cannot perform output normally to be likely to malfunction when the TFTs that should remain OFF are turned ON.
In order to prepare against the malfunction caused from the reason above, a conventional shift register receives pulse signals such as a clock pulse CK and a start pulse SP after the amplitude voltage of the pulse signals is increased by a level shifter to the level of the power supply voltage of the shift register.
A display device with a driving circuit that has a shift register including a level shifter is taken as an example here. The level shifter in this case may be formed on a substrate on which the driving circuit with the shift register and a pixel portion which receives signals outputted from the driving circuit to display an image are formed (this substrate is called a panel substrate). Alternatively, the level shifter may be formed on a single crystal IC substrate which is separate from the panel substrate.
If the level shifter is formed on a separate substrate from the panel substrate, circuits on the periphery of the pixel portion occupy a large area in the display device. In addition, power consumption is large because the wiring capacitance and wiring resistance are large at a connection portion between the level shifter and the circuits on the panel substrate.
On the other hand, if the level shifter is formed on the panel substrate, the following problem arises. Signal lines to which a clock pulse CK and a start pulse SP are inputted are large in load capacitance. Therefore, pulse signals such as a clock pulse CK and a start pulse SP are dulled in the buffer output after level shifting to cause timing deviation due to signal delay. In order to prevent the pulse signals from being dulled, the current supplying ability of the buffer has to be enhanced.
As described above, a shift register which has a level shifter formed on a panel substrate has problems such as difficulties in operating at high frequency, noises in power supply lines, and a large area for placement.
In order to increase the amplitude voltage of inputted pulse signals, a shift register can employ a level shifter formed on a panel substrate or a level shifter formed on a separate substrate from the panel substrate. In either way, however, the shift register has problems including difficulties in operating at high frequency, noises in power supply lines, and a large area for placement.